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| MC14557B 1-to-64 Bit Variable Length Shift Register The MC14557B is a static clocked serial shift register whose length may be programmed to be any number of bits between 1 and 64. The number of bits selected is equal to the sum of the subscripts of the enabled Length Control inputs (L1, L2, L4, L8, L16, and L32) plus one. Serial data may be selected from the A or B data inputs with the A/B select input. This feature is useful for recirculation purposes. A Clock Enable (CE) input is provided to allow gating of the clock or negative edge clocking capability. The device can be effectively used for variable digital delay lines or simply to implement odd length shift registers. http://onsemi.com MARKING DIAGRAMS 16 PDIP-16 P SUFFIX CASE 648 MC14557BCP AWLYYWW 1 16 SOIC-16 DW SUFFIX CASE 751G 1 16 14557B * * * * * * * 1-64 Bit Programmable Length Q and Q Serial Buffered Outputs Asynchronous Master Reset All Inputs Buffered No Limit On Clock Rise and Fall Times Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low-power TTL Loads or one Low-power Schottky TTL Load Over the Rated Temperature Range AWLYYWW MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 3.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value -0.5 to +18.0 -0.5 to VDD + 0.5 10 500 -55 to +125 -65 to +150 260 Unit V V mA mW C C C A WL, L YY, Y WW, W SOEIAJ-16 F SUFFIX CASE 966 1 MC14557B ALYW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device MC14557BCP MC14557BDW MC14557BDWR2 MC14557BF MC14557BFEL Package PDIP-16 SOIC-16 SOIC-16 SOEIAJ-16 SOEIAJ-16 Shipping 2000/Box 47/Rail 1000/Tape & Reel See Note 1. See Note 1. 2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. (c) Semiconductor Components Industries, LLC, 2000 1 August, 2000 - Rev. 4 Printed from www.freetradezone.com, a service of Partminer, Inc. Publication Order Number: MC14557B/D This Material Copyrighted by Its Respective Manufacturer MC14557B PIN ASSIGNMENT L2 L1 RESET CLOCK CE B A VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD L4 L8 L16 L32 Q Q A/B SEL BLOCK DIAGRAM 3 4 5 6 7 9 2 1 15 14 13 12 RESET CLOCK CE B A A/B SELECT L1 L2 L4 L8 L16 L32 VDD = PIN 16 VSS = PIN 8 Q 10 Q 11 TRUTH TABLE Inputs Rst 0 0 0 0 1 A/B 0 1 0 1 X Clock CE 0 0 1 1 X Output Q B A B A 0 X Q is the output of the first selected shift register stage. X = Don't Care LENGTH SELECT TRUTH TABLE L32 0 0 0 0 0 0 1 1 1 1 1 1 L16 0 0 0 0 0 0 0 0 1 1 1 1 L8 0 0 0 0 0 0 0 0 1 1 1 1 L4 0 0 0 0 1 1 0 0 1 1 1 1 L2 0 0 1 1 0 0 0 0 0 1 1 0 L1 0 1 0 1 0 1 0 1 0 1 0 1 Register Length 1 Bit 2 Bi Bits 3 Bits 4 Bits 5 Bits 6 Bits 33 Bit Bits 34 Bits 61 Bits 62 Bits 63 Bi Bits 64 Bits NOTE: Length equals the sum of the binary length control subscripts plus one. http://onsemi.com 2 Printed from www.freetradezone.com, a service of Partminer, Inc. This Material Copyrighted by Its Respective Manufacturer MC14557B Printed from www.freetradezone.com, a service of Partminer, Inc. This Material Copyrighted by Its Respective Manufacturer IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- 0.1 -- 5.0 10 20 - 2.4 - 0.51 - 1.3 - 3.4 0.51 1.3 3.4 -- -- -- -- -- - 4.2 - 0.88 - 2.25 - 8.8 0.88 2.25 8.8 0.00001 5.0 0.010 0.020 0.030 -- -- -- -- -- -- -- 0.1 7.5 5.0 10 20 - 1.7 - 0.36 - 0.9 - 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- 1.0 -- 150 300 600 Adc pF Adc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- - 55_C 25_C 125_C Max Min -- -- -- Typ (4.) 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current (5.) (6.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD IT IT = (1.75 A/kHz) f + IDD IT = (3.50 A/kHz) f + IDD IT = (5.25 A/kHz) f + IDD Adc 4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 5. The formulas given are for the typical characteristics only at 25_C. 6. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001. http://onsemi.com 3 MC14557B Printed from www.freetradezone.com, a service of Partminer, Inc. This Material Copyrighted by Its Respective Manufacturer IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C) Characteristic Rise and Fall Time, Q or Q Output tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Symbol tTLH, tTHL VDD 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 th 5 10 15 5 10 15 tr, tf tr, tf trem 5 10 15 5 10 15 5 10 15 -- -- -- 160 80 70 200 100 10 400 185 85 - 150 - 60 - 50 50 25 22 No Limit -- -- -- 80 40 35 15 5 4 -- -- -- s -- -- -- -- -- -- -- Min -- -- -- -- -- -- -- -- -- 200 100 75 300 140 100 -- -- -- 700 290 145 400 165 60 Typ (8.) 100 50 40 300 130 90 300 130 95 95 45 35 150 70 50 3.0 7.5 13.0 350 130 85 45 5 0 Max 200 100 80 600 260 180 ns 600 260 190 -- -- -- -- -- -- 1.7 5.0 6.7 -- -- -- -- -- -- ns ns Unit ns Propagation Delay, Clock or CE to Q or Q tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPLH, tPHL = (0.66 ns/pF) CL + 97 ns tPLH, tPHL = (0.5 ns/pF) CL + 65 ns Propagation Delay, Reset to Q or Q tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPLH, tPHL = (0.66 ns/pF) CL + 97 ns tPLH, tPHL = (0.5 ns/pF) CL + 70 ns Pulse Width, Clock tPLH, tPHL ns tPLH, tPHL tWH(cl) Pulse Width, Reset tWH(rst) ns Clock Frequency (50% Duty Cycle) fcl MHz Setup Time, A or B to Clock or CE Worst case condition: L1 = L2 = L4 = L8 = L16 = L32 = VSS (Register Length = 1) Best case condition: L32 = VDD, L1 through L16 = Don't Care (Any register length from 33 to 64) Hold Time, Clock or CE to A or B Best case condition: L1 = L2 = L4 = L8 = L16 = L32 = VSS (Register Length = 1) Worst case condition: L32 = VDD, L1 through L16 = Don't Care (Any register length from 33 to 64) Rise and Fall Time, Clock tsu ns Rise and Fall Time, Reset or CE Removal Time, Reset to Clock or CE ns 7. The formulas given are for the typical characteristics only at 25_C. 8. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. http://onsemi.com 4 MC14557B TIMING DIAGRAM 50% CLOCK VDD tWH(cl) 1/fcl 50% A INPUT tsu th RESET 1-bit length: CE = 0 Q A/B = 1 L1 = L2 = L4 = L8 = L16 = L32 = 0 tTLH 90% 50% 10% tTHL 50% PWR trem VSS VDD VSS VDD VSS VOH tPHL VOL tPLH tPHL http://onsemi.com 5 Printed from www.freetradezone.com, a service of Partminer, Inc. This Material Copyrighted by Its Respective Manufacturer CE CLOCK RESET 5 4 3 A 7 C R 32 BIT C R 16 BIT C 8 BIT R C 4 BIT R B 6 http://onsemi.com LOGIC DIAGRAM MC14557B A/B 9 SELECT 12 L32 13 L16 14 L8 15 L4 6 C 2 BIT R C 1 BIT R C 1 BIT R 10 Q 11 Q 1 L2 2 L1 VDD = PIN 16 VSS = PIN 8 MC14557B PACKAGE DIMENSIONS -A- 16 9 PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R B 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 F S C L -T- H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M SOIC-16 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G-03 ISSUE B D 16 M 9 A q NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 10.15 10.45 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ H B 1 16X 8 B TA S B B S 0.25 M A h X 45 _ SEATING PLANE M 8X 0.25 E A1 14X e T C http://onsemi.com 7 Printed from www.freetradezone.com, a service of Partminer, Inc. This Material Copyrighted by Its Respective Manufacturer L MC14557B PACKAGE DIMENSIONS SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O LE Q1 E HE 1 8 16 9 M_ L DETAIL P Z D e A VIEW P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.78 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.031 c b 0.13 (0.005) M A1 0.10 (0.004) ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. 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MC14557B/D This Material Copyrighted by Its Respective Manufacturer |
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